2022
INDENT: Incremental Online Decision Tree Training for Domain-Specific Systems-on-Chip Proceedings Article
In: Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 1-9, 2022.
Domain-Specific Architectures (DSAs): Research Problems and Promising Approaches Journal Article
In: ACM Transactions on Embedded Computing Systems (TECS), 2022.
2021
Anytime Depth Estimation with Limited Sensing and Computation Capabilities on Mobile Devices Proceedings Article
In: The Conference on Robot Learning, 2021.
FLASH: Fast Neural Architecture Search with Hardware Optimization Journal Article
In: ACM Transactions on Embedded Computing Systems, vol. 20, no. 63, pp. 1-26, 2021.
DAS: Dynamic Adaptive Scheduling for Energy-Efficient Heterogeneous SoCs Journal Article
In: IEEE Embedded Systems Letters, 2021.
2020
Runtime Task Scheduling Using Imitation Learning for Heterogeneous Many-Core Systems Journal Article
In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 11, pp. 4064-4077, 2020.
DS3: A system-level domain-specific system-on-chip simulation framework Journal Article
In: IEEE Transactions on Computers, 2020.
HiLITE: Hierarchical and Lightweight Imitation Learning for Power Management of Embedded SoCs Journal Article
In: IEEE Computer Architecture Letters, vol. 19, no. 1, pp. 63–67, 2020.
Runtime Task Scheduling using Imitation Learning for Heterogeneous Many-Core Systems Journal Article
In: arXiv preprint arXiv:2007.09361, 2020.
2019
Work-in-Progress: A Simulation Framework for Domain-Specific System-on-Chips Proceedings Article
In: 2019 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ ISSS), pp. 1–2, IEEE 2019.
Machine Learning-Based Processor Adaptability Targeting Energy, Performance, and Reliability Proceedings Article
In: 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 158–163, IEEE 2019.
2018
Machine learning and manycore systems design: A serendipitous symbiosis Journal Article
In: Computer, vol. 51, no. 7, pp. 66–77, 2018.
Learning-based application-agnostic 3D NoC design for heterogeneous manycore systems Journal Article
In: IEEE Transactions on Computers, vol. 68, no. 6, pp. 852–866, 2018.
Hybrid on-chip communication architectures for heterogeneous manycore systems Proceedings Article
In: 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 1–6, IEEE 2018.
2017
Imitation learning for dynamic VFI control in large-scale manycore systems Journal Article
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 9, pp. 2458–2471, 2017.
3D NoC-enabled heterogeneous manycore architectures for accelerating CNN training: performance and thermal trade-offs Proceedings Article
In: 2017 Eleventh IEEE/ACM International Symposium on Networks-on-Chip (NOCS), pp. 1–8, IEEE 2017.
On-chip communication network for efficient training of deep convolutional networks on heterogeneous manycore systems Journal Article
In: IEEE Transactions on Computers, vol. 67, no. 5, pp. 672–686, 2017.
2016
Hybrid network-on-chip architectures for accelerating deep learning kernels on heterogeneous manycore platforms Proceedings Article
In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, pp. 1–10, 2016.
nOS: A nano-sized distributed operating system for many-core embedded systems Proceedings Article
In: 2016 IEEE 34th International Conference on Computer Design (ICCD), pp. 177–184, IEEE 2016.
Communication-based design for nanoscale SoCs Book Section
In: The VLSI Handbook: Second Edition, pp. 16–1, CRC Press, 2016.
Performance evaluation of noc-based multicore systems: From traffic analysis to noc latency modeling Journal Article
In: ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 21, no. 3, pp. 1–38, 2016.
Wireless NoC and dynamic VFI codesign: Energy efficiency without performance penalty Journal Article
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 7, pp. 2488–2501, 2016.
2015
Energy efficient MapReduce with VFI-enabled multicore platforms Proceedings Article
In: 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 1–6, IEEE 2015.
Wireless NoC for VFI-enabled multicore chip design: Performance evaluation and design trade-offs Journal Article
In: IEEE Transactions on Computers, vol. 65, no. 4, pp. 1323–1336, 2015.
A support vector regression (SVR)-based latency model for network-on-chip (NoC) architectures Journal Article
In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 3, pp. 471–484, 2015.
Statistical learning in chip (slic) Proceedings Article
In: 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 664–669, IEEE 2015.
The (low) power of less wiring: Enabling energy efficiency in many-core platforms through wireless noc Proceedings Article
In: 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 165–169, IEEE 2015.
2014
A comprehensive and accurate latency model for network-on-chip performance analysis Proceedings Article
In: 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 323–328, IEEE 2014.
Low-latency wireless 3D NoCs via randomized shortcut chips Proceedings Article
In: 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1–6, IEEE 2014.
Energy-efficient VFI-partitioned multicore design using wireless NoC architectures Proceedings Article
In: Proceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, pp. 1–9, 2014.
Introduction to the special session on “Interconnect enhances architecture: Evolution of wireless NoC from planar to 3D” Proceedings Article
In: 2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), pp. 174–175, IEEE 2014.
An efficient network-on-chip (noc) based multicore platform for hierarchical parallel genetic algorithms Proceedings Article
In: 2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), pp. 17–24, IEEE 2014.
2013
A case for wireless 3D NoCs for CMPs Proceedings Article
In: 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 23–28, IEEE 2013.
Closed-loop control for power and thermal management in multi-core processors: Formal methods and industrial practice Proceedings Article
In: 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1879–1881, IEEE 2013.
Svr-noc: A performance analysis tool for network-on-chips using learning-based support vector regression model Proceedings Article
In: 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 354–357, IEEE 2013.
Fundamental limits on run-time power management algorithms for MPSoCs Book Section
In: Design Technologies for Green and Sustainable Computing Systems, pp. 1–21, Springer, New York, NY, 2013.
Dynamic power management for multidomain system-on-chip platforms: An optimal control approach Journal Article
In: ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 18, no. 4, pp. 1–20, 2013.
Performance evaluation of multicore systems: from traffic analysis to latency predictions (embedded tutorial) Proceedings Article
In: 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 82–84, IEEE 2013.
2012
A genetic algorithm based optimization method for low vertical link density 3-dimensional networks-on-chip many core systems Proceedings Article
In: NORCHIP 2012, pp. 1–4, IEEE 2012.
An optimal control approach to power management for multi-voltage and frequency islands multiprocessor platforms under highly variable workloads Proceedings Article
In: 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip, pp. 35–42, IEEE 2012.
Technology-driven limits on runtime power management algorithms for multiprocessor systems-on-chip Journal Article
In: ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 8, no. 4, pp. 1–17, 2012.
Dynamic power management for multicores: Case study using the intel SCC Proceedings Article
In: 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC), pp. 147–152, IEEE 2012.
A traffic-aware adaptive routing algorithm on a highly reconfigurable network-on-chip architecture Proceedings Article
In: Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, pp. 161–170, 2012.
Exploiting emergence in on-chip interconnects Journal Article
In: IEEE Transactions on Computers, vol. 63, no. 3, pp. 570–582, 2012.
2011
Towards a science of cyber-physical systems design Proceedings Article
In: 2011 IEEE/ACM second international conference on cyber-physical systems, pp. 99–108, IEEE 2011.
FARM: Fault-aware resource management in NoC-based multiprocessor platforms Proceedings Article
In: 2011 Design, Automation & Test in Europe, pp. 1–6, IEEE 2011.
Dynamic power management of voltage-frequency island partitioned networks-on-chip using intel's single-chip cloud computer Proceedings Article
In: Proceedings of the Fifth ACM/IEEE International Symposium, pp. 257–258, IEEE 2011.
Non-stationary traffic analysis and its implications on multicore platform design Journal Article
In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 4, pp. 508–519, 2011.
A software framework for trace analysis targeting multicore platforms design Proceedings Article
In: Proceedings of the Fifth ACM/IEEE International Symposium, pp. 259–260, IEEE 2011.