2003
Networks-on-chip: the quest for on-chip fault-tolerant communication Inproceedings
In: IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings., pp. 8–12, IEEE 2003.
Ambient intelligence visions and achievements: linking abstract ideas to real-world concepts Inproceedings
In: 2003 Design, Automation and Test in Europe Conference and Exhibition, pp. 10–15, IEEE 2003.
Modeling, analysis, and self-management of electronic textiles Journal Article
In: IEEE Transactions on Computers, 52 (8), pp. 996–1010, 2003.
Fault-tolerant techniques for ambient intelligent distributed systems Inproceedings
In: ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No. 03CH37486), pp. 348–355, IEEE 2003.
Application re-mapping for fault-tolerance in ambient intelligent systems Incollection
In: Ambient Intelligence: Impact on Embedded Sytem Design, pp. 315–335, Springer, Boston, MA, 2003.
Towards on-chip fault-tolerant communication Inproceedings
In: Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003., pp. 225–232, IEEE 2003.
2002
Traffic analysis for on-chip networks design of multimedia applications Inproceedings
In: Proceedings of the 39th annual Design Automation Conference, pp. 795–800, 2002.
System-level point-to-point communication synthesis using floorplanning information [soc] Inproceedings
In: Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design, pp. 573–579, IEEE 2002.
Challenges and opportunities in electronic textiles modeling and optimization Inproceedings
In: Proceedings 2002 Design Automation Conference (IEEE Cat. No. 02CH37324), pp. 175–180, IEEE 2002.
Challenges and Opportunities in Electronic Textiles Modeling, Analysis and Optimization Inproceedings
In: Int. Interactive Textiles for the Warrior Conf., 2002.
Does Q = MC/sup 2/? (On the relationship between Quality in electronic design and the Model of Colloidal Computing) Inproceedings
In: International Symposium on Quality Electronic Design: Proceedings: 18-21 March, 2002, San Jose, California, pp. 451, IEEE 2002.
On-chip communication analysis for multimedia applications Inproceedings
In: Proceedings. IEEE International Conference on Multimedia and Expo, pp. 185–188, IEEE 2002.
System and microarchitectural level power modeling, optimization, and their implications in energy aware computing Incollection
In: Power Aware Design Methodologies, pp. 241–276, Springer, Boston, MA, 2002.
2001
System-level power/performance analysis for embedded systems design Inproceedings
In: Proceedings of the 38th annual Design Automation Conference, pp. 599–604, 2001.
Probabilistic application modeling for system-level performance analysis Inproceedings
In: Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, pp. 572–579, IEEE 2001.
System-level power/performance analysis of portable multimedia systems communicating over wireless channels Inproceedings
In: IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No. 01CH37281), pp. 207–214, IEEE 2001.
2000
Low-power realizations of secure chaotic communication schemes Inproceedings
In: IEEE APCCAS 2000. 2000 IEEE Asia-Pacific Conference on Circuits and Systems. Electronic Communication Systems.(Cat. No. 00EX394), pp. 30–33, IEEE 2000.
Stochastic sequential machine synthesis with application to constrained sequence generation Journal Article
In: ACM Transactions on Design Automation of Electronic Systems (TODAES), 5 (3), pp. 658–681, 2000.
Improving simulation efficiency for circuit-level power estimation [CMOS] Inproceedings
In: 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No. 00CH36353), pp. 471–474, IEEE 2000.
Probabilistic aspects of crosstalk problems in CMOS ICs Inproceedings
In: Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No. 00CH37044), pp. 117–120, IEEE 2000.
Probabilistic analysis of power dissipation in VLSI systems. Journal Article
In: 2000.
1999
Sequence compaction for power estimation: Theory and practice Journal Article
In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18 (7), pp. 973–993, 1999.
Information-theoretic bounds for switching activity analysis in finite-state machines under temporally correlated inputs Inproceedings
In: Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers (Cat. No. CH37020), pp. 369–373, IEEE 1999.
Non-stationary effects in trace-driven power analysis Inproceedings
In: Proceedings of the 1999 international symposium on Low power electronics and design, pp. 133–138, 1999.
1998
Probabilistic modeling of dependencies during switching activity analysis Journal Article
In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 17 (2), pp. 73–83, 1998.
Theoretical bounds for switching activity analysis in finite-state machines Inproceedings
In: Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No. 98TH8379), pp. 36–41, IEEE 1998.
Trace-driven steady-state probability estimation in fsms with application to power estimation Inproceedings
In: Proceedings Design, Automation and Test in Europe, pp. 774–779, IEEE 1998.
1997
Adaptive models for input data compaction for power simulators Inproceedings
In: Proceedings of ASP-DAC'97: Asia and South Pacific Design Automation Conference, pp. 391–396, IEEE 1997.
Hierarchical sequence compaction for power estimation Inproceedings
In: Proceedings of the 34th annual Design Automation Conference, pp. 570–575, 1997.
Sequence compaction for probabilistic analysis of finite-state machines Inproceedings
In: Proceedings of the 34th annual Design Automation Conference, pp. 12–15, 1997.
Composite sequence compaction for finite-state machines using block entropy and high-order Markov models Inproceedings
In: Proceedings of 1997 International Symposium on Low Power Electronics and Design, pp. 190–195, IEEE 1997.
Vector compaction using dynamic Markov models Journal Article
In: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, 80 (10), pp. 1924–1933, 1997.
Steady-State Probability Estimation in FSM’s Considering High-Order Temporal Effects,’ Journal Article
In: Technical Report, 1997.
1996
Information theoretic measures for power analysis [logic design] Journal Article
In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15 (6), pp. 599–610, 1996.
Improving the efficiency of power simulators by input vector compaction Inproceedings
In: Proceedings of the 33rd annual Design Automation Conference, pp. 165–168, 1996.
Vector Compaction Using Hierarchical Markov Models Technical Report
Citeseer 1996.
Constrained Sequence Generation Using Stochastic Sequential Machines Journal Article
In: 1996.
1995
Efficient power estimation for highly correlated input streams Inproceedings
In: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference, pp. 628–634, 1995.
Information theoretic measures of energy consumption at register transfer level Inproceedings
In: Proceedings of the 1995 international symposium on Low power design, pp. 81–86, 1995.
Switching Activity Estimation Based on Conditional Independence Technical Report
Citeseer 1995.
RT-level power analysis using information theoretic measures Technical Report
USC Technical Report CENG 95-25 1995.
1994
Switching activity analysis considering spatiotemporal correlations Inproceedings
In: Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, pp. 294–299, 1994.
Logic Level Power Estimation Considering Spatiotemporal Journal Article
In: 1994.
1993
Worst-case analysis for pseudorandom testing Inproceedings
In: Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium, pp. 187–193, IEEE 1993.
0000
Pruning Digital Contact Networks for Meso-scale Epidemic Surveillance Using Foursquare Data Inproceedings Forthcoming
In: Forthcoming.
